Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices such as light emitting diodes, solar cells, or discrete diodes and transistors.
A p-n junction refers to a boundary or interface between two types of semiconductor material, p-type and n-type, inside a semiconductor. Advances in semiconductor technology have increased the requirements in measuring accuracy of the various characteristics of p-n junctions. Yield tracking and prediction requires reduced time to determine information of true electrical characteristics of devices being manufactured. Such characteristics may include current-voltage characteristics (I-V curves), sheet resistance and conductance measurements, leakage current measurements under reverse bias and forward voltage under forward bias, and the like. For instance, forward-voltage measured at 10 uA and 100 uA, as well as reverse current measured at −5V, are important manufacturing metrics for GaInN light-emitting diode (LED) manufacturers.
Currently, 4-point probe (4PP) techniques, such as the technique disclosed in U.S. Pat. No. 7,714,596, can be used for sheet resistance and conductance measurements by applying bias between top and bottom sides of wafers with p-n junctions. However, the existing 4PP techniques cannot be used for measurements of leakage current in GaInN LED structures on dielectric substrates such as sapphire. Another disadvantage of the existing 4PP techniques is that they are based on measurements of p-n junction conductance at very low reverse bias (<26 mV, also known as the linear regime where V<kT/q), which is not high enough for monitoring leakage current in GaInN LED structures in wide range of reverse bias (for example in the applied bias range 0 to −30V).
Other techniques for leakage measurements, such as those disclosed in U.S. Pat. App. No. 2013/0046496, U.S. Pat. App. No. 2013/0043875, and U.S. Pat. No. 7,679,381, use spring loaded probes to provide measurements of current-voltage characteristics (I-V curves). One of the main disadvantages of these techniques is related to the absence of any approach taking into account lateral current that strongly depends on the sheet resistance of p-n junction layers. This is critical because the lateral current leads to decreasing the current density, especially under reverse bias. Without knowing the current spreading, the current density is unknown. Other disadvantages of these techniques include severe measurement artifacts due to contact resistance as well as difficulties to contact the bottom layer of p-n junction grown on dielectric substrates such as sapphire.
Therein lies a need for systems and methods for accurate measurement and mapping of current-voltage characteristics under reverse as well as forward bias conditions of p-n junctions without the aforementioned shortcomings.